1. Field of the Invention
The present invention relates to an A/D converter for converting an analog signal into a digital signal. Particularly, an A/D converter with a high resolution of "X10 Mode" which is capable of providing a Ratio Metric Reading by cancelling an offset voltage in response to an application of a "Auto-Zero function.
2. Description of the Art
In general, a resolution of a dual slope integrating A/D converter employed in a Digital Multi-Meter (DMM) is 31/2 digits. But, in a dual slope A/D converter having a 31/2 digit resolution, a residual electric charge zero crossing can be charged by a capacitor of predetermined capacitance to multiply a voltage by ten times. The multiplied value is deintegrated again such that the resolution of the dual slope A/D converter is 41/2 digits or more.
The above mentioned mode is called "X10 Mode". A conventional dual slope integrating A/D converter applying the X10 Mode is shown in FIG. 1A. This converter comprises input portion 1, A/D core portion 2, and digital portion 3.
For a voltage measurement, input portion 1 will include mainly two switches S.sub.1 and S.sub.2 and a reference voltage .+-.V.sub.REF as shown in FIG. 1B. For a resistance measurement, input portion 1 will include mainly a supply power source, switches S.sub.3 to S.sub.8, a reference resistor R.sub.fef, a capacitor C.sub.x, and a measured resistor R.sub.x as shown in FIG. 1C.
A/D core portion 2 comprises a buffer BF, and operational amplifier (OP AMP), a comparator CM, switches S.sub.9 to S.sub.11, a resistor R.sub.1, and a capacitor C.sub.1 to C.sub.3.
As shown in FIG. 1D, digital portion 3 comprises a clock signal input portion 4, a zero crossing detecting portion 5, a logic control portion 6, a decoder/resistor 8, and a drive/display portion 9.
The conventional dual slope A/D converter comprising the above-mentioned constituent elements for performing a voltage measurement operation, connects the portion measuring voltage between a power source terminal V and a common terminal Acom in FIG. 1B. Reference voltage .+-.V.sub.REF is employed as the voltage for discharging the electric charge charged by integrating capacitor C.sub.1 of A/D core portion 2 shown in FIG. 1A by way of the common terminal. In this manner, the discharged electric charge quantity can be regulated.
If a measured voltage C.sub.IN has a negative polarity, a reference voltage .+-.V.sub.REF is supplied, and if the measured Voltage V.sub.IN is a positive polarity, a reference voltage -V.sub.REF is supplied.
For performing a resistance measurement, input portion 1 resembles a ratio metric reading circuit. A supply power source V.sub.s, a reference resistor R.sub.ref, a resistance measuring portion (that is, resistor R.sub.x), and common terminal A.sub.COM are all connected in series as shown in FIG. 1C. As a current flows through this series circuit, a voltage drop across reference resistor R.sub.ref will be represented as V.sub.ref and a voltage drop across resistor R.sub.x will be represented as V.sub.x.
Reference resistor R.sub.ref is connected to capacitor C.sub.x through switches S.sub.3 and S.sub.4. One terminal of capacitor C.sub.x is connected to an output terminal LO through switch S.sub.5. The other terminal of capacitor C.sub.x is connected to an output terminal HI through switch S.sub.6.
As input terminal R is connected to output terminal HI through switch S.sub.7 and terminal A.sub.com is connected to output terminal LO through switch S.sub.8, the voltage charge in capacitor C.sub.x is deintegrated.
On the other hand, the conversion operation is performed by a conversion cycle defined as shown in FIG. 2. The conversion cycle includes a zero integration phase Z1, an integration phase INT, a first deintegration phase DE1, a REST phase, X10 phase, and a second deintegration phase DE2.
In order to display the difference between the value converting the offset voltage and the value converting the following input V.sub.IN (the measured voltage), first the power source terminal V must be shorted at the common terminal (that is, the zero reading). Then it can receive the input V.sub.IN.
Let us define the operating time during zero integration phase ZI as T.sub.ZI. During a voltage measurement operation, if switches S.sub.9 and S.sub.10 of A/D core portion 2 in FIG. 1A are closed during zero integration phase Z1, the voltage V.sub.o at node P during zero integration phase Z1 can be expressed by the following equation. ##EQU1## Therefore, you will find that the voltage V.sub.o at node P varies with a change in T.sub.zI.
Let us now define the operating time during integration phase INT as T.sub.INT.
If switch S.sub.1 in FIG. 1B is closed during integration phase INT, a current will flow through buffer BF, resistor R.sub.1 and capacitor C.sub.1 of A/D core portion 2 in FIG. 1A. As a result, the voltage V.sub.o at node P is changed. At this time, the change (.DELTA.V.sub.o) is expressed by the following equation: ##EQU2## The first deintegration phase DE1 is operated from the application of reference voltage -V.sub.REF till the beginning of the zero crossing.
Let us define the operating time in first deintegration phase DE1 as T.sub.DE1. The change (.DELTA.V.sub.o) of voltage V.sub.o at node P can be expressed by the equation: ##EQU3## The amount of voltage change at the moment a zero crossing becomes "0" can be expressed by the equations: EQU V.sub.o .vertline.T.sub.INT +V.sub.o .vertline.T.sub.DE1 =0 (4)
and ##EQU4## In Eq. 5, if reference voltage (V.sub.REF) is regulated and V.sub.REF +V.sub.os1 -V.sub.os2 equals V.sub.REF', Eq. 5 can be expressed by the equation: ##EQU5## Therefore, if a zero reading is performed first and ##EQU6## the offset voltage can be cancelled by T.sub.DE1 -T.sub.DE (zero reading).
That is, T.sub.DE is expressed by the equation. ##EQU7## where V.sub.REF' equals V.sub.REF +V.sub.os2, and T.sub.INT is a fixed time.
Next, let us define the operating time during the REST phase as T.sub.REST. If switch S.sub.9 of A/D core portion 2 in FIG. 1A is closed during the REST phase, the residual electric charge stored in capacitor S.sub.3 will be kept during the REST phase.
At this time, the voltage across capacitor C.sub.1 becomes the same voltage as that across capacitor C.sub.3.
During the X10 phase, switch S.sub.10 of A/D core portion 2 is closed and switch S.sub.11 is opened. Then, the output of comparator CM is fedback to buffer BF and operational amplifier OP AMP as the residual electric charges in capacitor C.sub.3 is transferred to capacitor C.sub.2. The multiplied voltage at node P varies with the capacitance of capacitors C.sub.2 and C.sub.3.
As the capacitance of capacitor C.sub.3 reaches a value ten times greater than the capacitance of capacitor C.sub.2, the voltage applied across capacitor C.sub.2 becomes ten times greater than that across capacitor C.sub.3.
The Second integration phase DE2 discharges the multiplied voltage V.sub.o at node P and counts the time for zero crossing to begin. As the counted time and time T.sub.DE1 for first deintegration phase DE1 is calculated, a resolution of X10 can be obtained.
The operating condition of the switches in each conversion cycle is shown by the following table 1.
TABLE 1 ______________________________________ The operating condition of the switches during each conversion cycle: Drawings FIG. 1A FIG. 1B FIG. 1C Switch Phase S.sub.9 S.sub.10 S.sub.11 S.sub.1 S.sub.2 S.sub.3 S.sub.4 S.sub.5 S.sub.6 S.sub.7 S.sub.8 ______________________________________ ZI C C C O O C C O O O O INT O O C C O C C O O C C DE1 O O C O C O O C C O O REST C O C O O C C O O O O X10 O C O O O C C O O O O DE2 O O C O C O O C C O O ______________________________________ C represents a switch is closed, and O represents a switch is opened.
Up to now we have described the operation for a voltage measurement operation. A conversion cycle for a resistance measurement operation progresses very much like that for a voltage measurement operation.
For a resistance measurement operation, during the zero integration phase Z1, the measuring register R.sub.x is connected between input terminal R and common terminal ACOM as shown in FIG. 1C such that supply power source V.sub.s is applied through reference resistor R.sub.ref. The current I.sub.s through measuring resistor R.sub.x is therefore expressed by the following equation: ##EQU8##
Switches S.sub.5 and S.sub.6 are closed during the integration phase INT such that voltage V.sub.x applied across measuring resistor R.sub.x is integrated.
Voltage V.sub.REF applied across reference resistor R.sub.REF in FIG. 1C is expressed by the equation: ##EQU9##
Switches S.sub.5 and S.sub.6 are closed during the first deintegration phase DE1 such that voltage V.sub.o at node P integrated by voltage V.sub.x is discharged again.
The first deintegration phase DE1 is operated until the zero crossing begins. At this point, T.sub.DE1 is calculated during the first deintegration phase DE1. T.sub.DE1 is expressed by the equation: ##EQU10## It should be noted that ##EQU11## varies in response to a change of measuring resistor R.sub.x. Therefore, although it provides the zero reading, the offset voltage V.sub.os1-V.sub.os2 is not cancelled.
The conventional dual slope A/D converter has the following problems.
The conventional dual slope A/D converter operating as mentioned above is in need of a zero reading step, therefore the conversion time during each conversion cycle is lengthened. As a result, its operating speed is slow. Further, as the offset voltage is not completely cancelled in a ratio metric reading, it is very difficult to obtain high resolution.